It is necessary to know precisely a so-called “bit time” during the synchronous transmission of serial digital data in baseband. The bit time is the period of time during which each individual bit of data is transmitted and travels on the communication channel. The bits are transmitted in series and travel in the form of pulses. Further, each pulse occupies (at least theoretically) its own elemental time interval (“time slot”), which is also called a “unitary interval” or “UI”. The duration of this elemental time interval is the reciprocal of the data-transmission rate (i.e, the data rate).
After normal processing for automatic equalization and squaring, the received signal is in the form of square pulses. In order to reconstruct the value of an individual bit of data arriving on the communication channel, the receiving circuits have to know precisely the moment at which the bit arrives, i.e., the moment of arrival of the pulse that corresponds to the bit.
Data codes of various types are used in semi-duplex serial transmission. When the shape of the signal within the time domain and its spectral content are processed by the receiving circuits, they can identify the moment in time at which the arriving pulse should be evaluated as the value of the arriving bit of data. The process of identifying the moment at which to evaluate the pulses is called clock data recovery (CDR).
There are various known prior art methods of recovering clock data. A summary of these methods is provided, for example, in B. Razavi, “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial”, IEEE Press, 1995. These methods are described with reference to applications in which the data is transmitted in baseband with non-return-to-zero (NRZ) code. In particular, the use of circuits for switching between a plurality of digital phase signals to identify and follow the timing of the data received is described.
In addition to the NRZ code, another type of code which is known and used in the synchronous serial transmission of digital data in baseband is code mark inversion (CMI) code. CMI code is used, for example, within the field of synchronous data transmission in accordance with the synchronous digital hierarchy (SDH) standard. The SDH standard prescribes predetermined transmission rates, for example: 51.84 Mbit/s (base rate), 155.52 Mbit/s, 622.08 Mbit/s, etc. All of the prescribed transmission rates are whole multiples of the base rate.
In accordance with the SDH standard, Recommendation G.703 issued by the CCITT committee of the International Telecommunication Union (ITU) prescribes the electrical/physical characteristics of the hierarchical digital interfaces to be used to interconnect components of digital networks which conform to the SDH standard. In particular, Recommendation G.703 prescribes the type of data code to be used for each transmission rate. For example, for 155.52 Mbit/s transmission/receiving interfaces (also known as bidirectional or transceiver interfaces), CMI code should be used.
CMI code is a code with two levels A1 and A2. These levels are typically low and high, and a binary “0” is encoded to have the two levels A1 and A2, in succession, each for a period equal to half of the bit-time. A binary “1” is encoded by one or the other of the two levels A1 or A2, which is maintained throughout the bit time. The two levels A1, A2 alternate for successive binary “1”s.
CMI code intrinsically incorporates a strong clock signal. The known solutions for clock data recovery for codes which intrinsically carry a strong clock signal provide for an analog phase-locked loop (PLL) circuit. This PLL circuit operates at a frequency of twice the data transmission rate (the data rate) to be able to control the content at twice the intrinsic frequency of the CMI code.
It is also known in the art to use digital PLL circuits which use a rapid clock signal or a multi-phase local clock signal. This signal is a signal which includes a plurality of clock signals out of phase with one another in time. Such PLL circuits may also follow the data received and dynamically select the best phase for sampling the data. Such a circuit is known by the name of a phase-switching CDR circuit. It includes a switching circuit which receives as inputs a number N clock signals or synchronism phases spaced at regular time intervals. This circuit can select which of the phases is best for use as a synchronism signal for sampling the next bit of data.
In these circuits, however, there exists a problem in preventing the production of false signals or glitches caused by spurious transitions. Such false signals could cause incorrect sampling of the incoming bit of data during the change from one phase to the phase following or preceding it in terms of time delay. This gives rise to vibrations (i.e., jitter) in the recovery of the arriving clock data.